PCB Chat 161: Chris Parker Discusses Case Study on Dielectrics and Thermal Management

Andy Shaughnessy (0:05)

26 degrees, that is how much cooler a power component ran when the only thing that changed was the material underneath it. No bigger heat sink, no extra copper, no redesigned layout, just the dielectric. A controlled study at the Rochester Institute of Technology measured it, and today we are going to unpack exactly how that happened and what it means for the way you design boards. This is PCB Chat.

Hey everybody, I am Andy Shaughnessy. If you have been around the PCB design world for any length of time, chances are pretty good we have crossed paths. Maybe at a conference, maybe you have read one of my articles, or maybe you have just seen me wandering the show floor with a microphone trying to get somebody to talk to me.

I have been covering this industry for over 20 years now, and I have to tell you, the thermal management conversation has changed more in the last few years than in the previous two decades combined. The power densities designers are dealing with today, they are just brutal, and the old playbook is not keeping up. So when I got a look at the data behind what we are going to talk about today, I thought, well now we have got to dig into this one.

Now before I bring my guest in, let me take a quick second to thank the sponsor who made today's episode possible. And I will be honest with you, it could not be a better fit. Today's episode of PCB Chat is brought to you by FLIR. Now, if you have ever needed to actually see where the heat is hiding on a board, then you already know FLIR. Their thermal imaging cameras are a staple in electronics labs all over the world. And here is the fun part. That controlled study Chris and I are about to dig into, all of that beautiful temperature data, it was captured with a calibrated FLIR camera. So when you hear those numbers here in a few minutes, well, that is FLIR doing the seeing. To learn more about thermal imaging for electronics design and test, go visit FLIR online. All right, with that, let us get into it.

My guest today is Chris Parker, Senior Applications Engineer at Tclad Inc. Chris has about 30 years of thermal design experience in this industry, and he has been leading the work behind Tclad's SFL-12 platform, including the validation programs at RIT and CoolCAD Electronics. Chris, it is great to have you on, my friend.

Chris Parker (2:33)

Andy, thanks for having me. I have been a fan of your work for a long time, so this is a good one for me.

Andy Shaughnessy (2:40)

Well, I appreciate that very much, and I am really looking forward to this, because I think what you all are doing challenges some assumptions that have been baked into this industry for a very, very long time.

So let me kick things off with the big picture. For decades, the PCB has basically been treated as the thing that connects components electrically, right? And then thermal management gets bolted on after the fact. Heat sinks, copper coins, fans, thermal vias. Why is that approach starting to hit a wall?

Chris Parker (3:17)

Because we have been working around the real problem instead of solving it. The dielectric, that is the insulating layer between your copper planes, is the thermal bottleneck in most multilayer boards.

FR-4 has a thermal conductivity of about 0.3 to 0.4 watts per meter Kelvin. Copper is around 400 So there is this massive mismatch sitting right in the middle of your stack up.

Andy Shaughnessy (3:47)

Oh, man. So you have got all this beautiful copper that is great at conducting heat, but the layer sandwiched in between is basically acting like a thermal blanket. Just sitting there blocking the path.

Chris Parker (3:59)

Exactly. You can pour copper into your design all day, thicker planes, more vias. But if the heat cannot move vertically through the dielectric to actually reach those copper layers, you are not spreading anything. You are insulating. And that was tolerable when power densities were lower. But look at what is happening now.

EV power stages, GAN and SIC devices, AI accelerator power delivery. The current densities in these designs are climbing fast. And the dielectric wall is where every one of them hits.

Andy Shaughnessy (4:37)

You know, I talk to designers all the time at these conferences, and I hear this frustration constantly. They are doing everything they can with copper and VIAs and still fighting hotspots.

So let me put this in plain terms for anybody listening who is not neck deep in thermal math every day. Chris, you are basically saying the material that most of the industry just takes for granted, the thing nobody even thinks to question, is actually the single biggest limit on how much heat your board can handle. Is that fair?