Nvidia Weighs Glass Substrates to Stack More HBM on AI Chips - Seoul Economic Daily

Skyler Monroe (0:10)

Hey, everyone, welcome back to The AI Hardware Show. I'm your host, Skyler Monroe. And if you're into the Silicon, the servers and the science powering the AI revolution, you are in exactly the right place. Huge thank you to our sponsors keeping the show going. Ada, helping businesses actually integrate AI into their workflows in ways that make sense. Ago Consulting, that's Ago, your go-to for Silicon Development Consulting. Whether you're working on AI chips or full-socks designs, and Zen Semiconductor, the umbrella company building the hardware backbone of modern AI, from their Sierra RISC VCPUs to their Loom AI fabric, plus Ada for deploying AI at scale.

Seriously, great companies, check them out. All right, today we've got a packed episode. Nvidia is eyeing some seriously cool new packaging tech, involving Glass. Google is literally sending TPUs into space. There's some spicy news about H200 chips heading to China, and we're diving into what's driving the semiconductor equipment market right now. Let's get into it. Okay, first up, Nvidia is apparently exploring the use of glass substrates to help stack more HBM memory on their AI chips. And this one caught my eye because it's a packaging story. And packaging is honestly one of the most underappreciated battlegrounds in AI hardware right now. So let's break this down. When we talk about AI chips, your H100s, your B200s, whatever comes next, the raw compute die is only part of the story.

The memory sitting next to it matters enormously. HBM, which stands for High Bandwidth Memory, is the super fast memory stacked up beside the compute die. And the amount of HBM you can fit and how fast it can talk to the chip is often the real bottleneck for AI performance. Now here's the thing. Right now, the substrate that holds all of this together is typically made of silicon. You've got your compute dies, your HBM stacks, all sitting on what's called an interposer. Basically a really sophisticated platform that routes all the electrical connections between everything.

Silicon interposers work well, but they have limitations. They're expensive to manufacture, and there are physical constraints to how large you can make them, and how densely you can pack everything in.

Glass substrates are being floated, pun intended as a potential upgrade here, and there are some genuinely compelling reasons why.

Glass has some really nice electrical properties. It has lower signal loss, which means data can move between components with less interference and at higher speeds. It also has better dimensional stability, meaning it doesn't warp or expand as much with heat changes, which matters a lot when you're talking about incredibly precise chip-to-chip connections at microscopic scales. Think of it like this. If silicon interposers are a wooden cutting board, glass substrates are a perfectly flat marble slab. More stable, smoother, and better for precise work. For Nvidia, the potential benefit is being able to stack more HBM, possibly more stacks, possibly taller stacks, which would mean dramatically more memory capacity and bandwidth on a single package. That's huge for AI training workloads, which are absolutely memory hungry. The more memory bandwidth you have, the faster you can feed data to those thousands of CUDA cores crunching through model weights. Intel has been talking about glass substrates for a while through their research programs, and now it sounds like Nvidia is seriously kicking the tires on this for future chips. This isn't something you'll see in the next product cycle. This is longer term roadmap stuff, but it signals where the industry is heading. As compute dies get bigger and HBM stacks keep growing, the packaging holding it all together has to evolve too. The chip isn't just the chip anymore, it's the whole system in a package, and the substrate is a critical piece of that puzzle. Keep your eyes on this one, because glass substrates could genuinely be a quiet revolution in how AI chips are built. Alright, story number two, and I have to say, this one made me do a double take. Google is launching a satellite into orbit, and it's got four TPUs on board. Yes, tensor processing units, in space. Let me just let that sink in for a second. So Google has been developing their TPU-line tensor processing units for years now and their purpose built for AI workloads. They power a huge chunk of Google's internal AI infrastructure and are available through Google Cloud. They're incredibly efficient at the specific types of matrix math that neural networks love, but space, that's a new frontier, literally. According to the report, Google is launching an experimental satellite that will carry four TPUs and about 1,000 watts of solar power generation capability. Now, 1,000 watts of solar in orbit is actually a meaningful amount. Solar panels in space don't have to deal with atmospheric absorption, so they're more efficient than ground-based panels, but it's still a relatively constrained power budget for serious compute. So this is clearly an experimental payload, not a production system. So why would you want AI compute in orbit? A few reasons, and they're all pretty interesting. The biggest one is latency and data volume. Earth observation satellites generate absolutely massive amounts of data, imagery, radar, spectral data, and right now, most of that data has to be beamed down to ground stations before you can do anything with it. That takes time and consumes precious bandwidth. If you can do AI inference right on the satellite, analyzing imagery, detecting anomalies, classifying what you're seeing, you can send down only the useful results instead of raw data dumps. That's a massive efficiency gain. Think of it like the difference between streaming an entire raw video feed versus having a smart camera that only sends you an alert when it sees something interesting.