AMD EPYC Venice Sold Out & the CPU Bottleneck Reshaping AI Data Centres

Jamie Cole (0:00)

Our Hardware & Chips Daily News.

I'm Jamie Cole. Thanks for joining me.

Today, the CPU supply shock, why agents need more cores than GPUs.

All of AMD's EPYC Venice production through 2027 is gone. Every unit, fully allocated. Buyers who missed the window are now booking 2028 delivery at premiums north of 40%.

That's not a demand signal. That's a supply crisis. And it tells us something important about where AI infrastructure is actually heading. The conventional assumption has been that GPUs are the constraint in AI buildouts. More compute, more memory bandwidth, more accelerators. That framing made sense when the workload was training large models or running batch inference. But agentic AI changes the equation in a way that most infrastructure planning hasn't caught up with yet. Here's what the research is now quantifying. Workout of Georgia Tech and Intel put CPU side orchestration at somewhere between 50% and 90% of end-to-end latency in agentic systems. These are workloads where an AI model doesn't just generate a response. It calls tools, retrieves data, manages state, coordinates subagents, and loops back. All of that orchestration runs on CPUs, not GPUs. The implication is direct. Course per gigawatt demand is projected to jump from 30 million to 120 million, a four times increase. That inversion matters because it reorders every procurement priority in a modern data center. GPU capacity you already have, CPU capacity it turns out you don't.

AMD's Venice is the chip that was supposed to relieve that pressure. It's the first high-performance computing product in volume production on TSEC's N2 nanosheet process. The architecture runs 16 DDR5 channels, delivering 1.6 terabytes per second of memory bandwidth. That bandwidth matters specifically for retrieval-heavy agentic workflows, where data access patterns are irregular and latency-sensitive. Morgan Stanley puts the revenue picture at roughly $51 billion in 2027 AMD's server CPU visibility alone, based on 6.75 million units at a blended average selling price around $7,700.

The signal here is that this isn't a niche server refresh, it's a generational platform transition happening into a supply vacuum. Here's the thing. The important distinction is that Venice's availability still depends on how TSMC allocates its N2 capacity. The target is 120,000 waivers per month by end of 2026

Apple, AMD, Nvidia and Qualcomm are all competing for that output. How that allocation resolves hasn't been publicly disclosed, and until it is, actual Venice shipment volumes carry real uncertainty.

The memory side of this story deserves attention too. Samsung has confirmed that HBM will rise to 30% of its DRM fab capacity by 2027, up from 20% now. Each BM production consumes roughly three times the wafer area of conventional DRAM per bit. The arithmetic compresses conventional DRAM supply significantly, and that shortage extends to standard server memory, not just AI accelerator stacks. The practical effect is that two separate memory constraints are developing in parallel. One for AI training and inference hardware needing HBM, one for the CPU-heavy Agentsic infrastructure needing dense, fast conventional DRAM. One piece of new capacity is now online. VIS has opened Singapore's first 300mm fab, built with TSMC-licensed interposer technology. First phase capacity is already pre-sold, entirely to AI packaging customers. Where the second phase commitment follows is still open. Consider this. Intel posted 25% revenue growth to $16.1 billion in its latest quarter, with positive operating margins returning. The catch is adjusted free cash flow at negative 8.4 billion, driven by expansion capital expenditure. The margin recovery is real, the cash burn is also real. Those two facts sit together uncomfortably, and investors watching Intel's Foundry ambitions should treat profitability as a future test, not a current outcome. The through line across all of this is that AI infrastructure constraints have shifted. GPU allocation was the defining bottleneck of 2023 and 2024 CPU supply, advanced packaging, and conventional DRM are becoming the binding constraints of 2027 and beyond. The metrics that matter from here, TSMC's N2 allocation disclosure, independent Venice performance benchmarks expected in the fourth quarter of 2026, and whether Samsung's HBM capacity expansion delays or accelerates conventional DRM recovery, those three data points will tell you more about where AI infrastructure actually lands than any product announcement.

Thanks for listening. This podcast was built using AI technology. A YesWe production.