CoWoS Doubling, Intel EMIB-T & CIA-Beijing Escalation
AI Hardware & Chips: Daily News
September 13, 2026
(00:00:00) CoWoS Doubling, Intel EMIB-T & CIA-Beijing Escalation (00:01:02) TSMC Capacity Doubling Plan (00:01:39) Intel EMIB-T Enters the Race (00:02:24) HBM Yield as Hidden Bottleneck (00:03:02) CIA Targets, Beijing Responds (00:03:42) Summit Stakes and Supply Chain Signals The AI hardware supply...
Speakers Jamie Cole
Jamie Cole (0:00)
A Hardware & Chips Daily News.
I'm Jamie Cole, thanks for joining me. Today, the packaging crunch, why CoOS now matters more than 3nm.
TSMC just confirmed its doubling CoOS packaging capacity to 260,000 wafers per month by end of 2028 And that single announcement tells you more about where the AI supply chain is actually breaking than anything happening at the leading edge node. Here's the key distinction. For the past few years, the conversation around AI hardware has been dominated by lithography.
3nm, 2nm, ASML Extreme Ultraviolet tools.
But the binding constraint in 2026 isn't going to be which fab can print the smallest transistor. It's going to be whether anyone can package the chips that already exist into systems that actually work at scale. CoO, which stands for chip-on-wafer-on-substrate, is the technology that lets you bond high bandwidth memory directly to a GPU or AI accelerator on a silicon interposer. Without it, you don't get an H100, you don't get a B200. You get a fast chip sitting in a slow system. That's the constraint that matters now. TSMC currently runs about 130,000 CoOs wafers per month. The plan is to reach 260,000 by 2028, with expansion happening across its AP7 facility in Taiwan and its Arizona operations.
The trajectory is clear. The execution risk is real. Any slip in the Arizona ramp or the AP7 timeline extends the supply gap directly into AI accelerator delivery schedules. Nvidia's customers feel that delay. Hyperscalers feel it. The supply chain for AI compute is only as fast as its slowest integration step. And right now, that step is packaging. Intel is not standing still. Its Emib-T packaging technology is estimated to reach 40,000 to 45,000 wafers per month by 2028 That's a fraction of where TSMC will be, but it's a real number. The important distinction is that Intel's path gives customers an alternative qualification target, which changes the competitive dynamic even before Intel closes the capacity gap. Here's the thing. Where the customers will actually qualify Emib-T at volume is still an open question. Technical differences between the approaches are real, and qualification cycles are long.
But the existence of a credible second option matters for negotiating leverage and supply chain resilience, even if adoption rates stay modest through this cycle.
Packaging capacity isn't the only constraint running parallel to the node conversation. HBM4 yield heat dissipation and stacking reliability are all limiting factors in AI accelerator production cadence heading into 2026
There are no public forecasts on how fast HBM4 yield ramps. That absence of data is itself a signal worth tracking. The system level picture is this. Competitive advantage in AI hardware is no longer about who leads on process node alone. It flows from integrated execution across chip design, packaging, memory and thermal management. That's a harder capability to build, and a harder lead to close. On the geopolitical side, a confrontation that's been building quietly just became public. The CIA director named Chinese AI and semiconductor companies as explicit intelligence collection priorities. Beijing's formal response was to invoke its expanded 2023 counter-espionage law as a direct threat against US companies operating in China. Consider this. The law was already used against Mintz Group and Bain. Its language is broad and deliberately interpreted that way. For US chip firms with China operations, this isn't an abstract legal warning. It's operational risk, and it's now formally on the table, ahead of a scheduled September 24th summit between Trump and Xi. That summit is the next real watchpoint. The outcome could reset semiconductor trade barriers or harden them further. Either direction accelerates or complicates the geographic consolidation of packaging capacity outside Taiwan. TSMC's Arizona expansion is partly a hedge against exactly this kind of geopolitical friction. The signal here is that backend packaging. Memory Yield and US-China Legal Risk are now operating in the same strategic frame. Watch the summit, watch the HBM4 yield data when it surfaces, and watch whether Intel's Emib-T picks up any customer qualification momentum. Those are the metrics that will define the AI hardware supply picture through 2026 and beyond.
Thanks for listening. This podcast was built using AI technology, a Yes We production.
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