TSMC's $265B Bet: CoWoS Crunch, Memory Sold Out & UAE Chip Access

**Jamie Call** (0:00)
A Hardware & Chips Daily News.
I'm Jamie Call. Thanks for joining me.
Today, CoWoS Packaging. TSMC's chief executive just said out loud what the supply chain has been showing for months. The bottleneck in AI hardware isn't wafer production anymore. It's packaging. That's the signal worth pulling from an otherwise record-setting earnings report. Wevenu came in at $40.2 billion for the second quarter, up 36% year-on-year.
Four-year growth guidance now sits above 40%.
These are not incremental numbers. But buried inside that headline performance is a constraint that reshapes how you think about AI infrastructure capacity.
CoWo, which stands for chip on wafer on substrate, is TSMC's proprietary advanced packaging technology. It's what binds AI accelerators together with high bandwidth memory at the densities required for large model training and inference.
Without it, the chips don't perform at the level hyperscalers need. And right now, lead times for CoWo have stretched to between 52 and 78 weeks. Here's what that shift means in practice. The conversation in this industry has been dominated by node progression. 2 nanometer yields, 3 nanometer capacity. How fast TSMC can ramp an N2? That framing is now secondary. CEO CC. Wei explicitly acknowledged that advanced packaging lead times are limiting customer growth more than logic production itself. When the Foundry's own chief executive reorders the constraint hierarchy, that's worth taking seriously. The implication is structural. Even if TSMC accelerates N2 wafer output, it doesn't move the delivery timeline for a customer waiting on a CoWoS packaged AI accelerator. The BottleMeek migrates downstream, and customers can't outrun it by throwing more orders at the FAT. TSMC hasn't disclosed how much Capex it's directing specifically toward CoWoS expansion, and that's the missing number. Competitors like Intel, with its EMIB interconnect technology, and Samsung are reportedly two to three years behind on comparable packaging capability, so there's no near-term external relief. The packaging constraint doesn't sit alone. Memory is now equally tight. Draymond NAND supply is sold out through 2027 Micron is reportedly meeting only 50 to 67% of core customer demand. New fab capacity for memory manufacturers isn't expected to arrive in meaningful volume until late 2027 into 2028 Here's the thing. The key implication is that two separate supply chains, packaging and memory, are now simultaneously binding AI infrastructure deployment.
Demand isn't the limiting variable. Customers want more capacity. Hyperscalers would absorb it immediately. The constraint is physical supply, and it runs deep. On the investment side, TSMC added another $100 billion to its Arizona commitment, bringing the total to $265 billion.
Capital expenditure guidance for 2026 was raised to between $60 and $64 billion.
These are very large numbers, and the question they raise is straightforward. Does geographic diversification actually solve capacity, or does it relocate the same shortage to a different location? That remains genuinely unresolved. US fab construction moves slower than Taiwan or Japan, and packaging infrastructure in Arizona is still early stage. The commitment signals confidence in multi-year demand. Whether it relieves the current crunch is a different question entirely.
Away from TSMC's earnings, the US Commerce Department elevated the UAE to A5 classification, granting license-free access to advanced Nvidia chips. The immediate beneficiary is the Stargate UAE data center project, a $30 billion joint venture targeting 5 gigawatts of AI compute capacity. That's a significant diplomatic signal. The US is now actively using semiconductor access as an alliance-building instrument, elevating Gulf partners toward the same tier as Mato Allies while tightening restrictions elsewhere. Consider this. The enforcement mechanisms around the A5 classification remain unclear, and the rule is subject to review after nine months. That's an uncertainty worth tracking. The near-term signals to watch are specific. First, whether TSMC discloses targeted CoWoS Capex in its next investor communications. That's the number that would indicate how seriously it's treating packaging as a first-order problem rather than a footnote. Second, any update from Micron or Samsung on memory capacity timelines. A pull forward of new DRAM supply would meaningfully change the system-level picture. Third, N2 Yield Economics. TSMC reported $1.21 billion in 2nm revenue at 3% of total wafer share, with AMD's Venice EPYC CPUs driving early volume. The cost structure and yield rates haven't been disclosed. That transparency matters for anyone trying to model when N2 becomes a volume node rather than a premium ramp. The story here isn't the record revenue. It's that the ceiling on AI hardware deployment is now set by integration in memory, not by how fast fabs can print silicon. That's a meaningful refrain, and it's one the industry is still catching up to. Thanks for listening. This podcast was built using AI technology, a Yesui production.