Intel 18A Yields, EMIB-T Breaks CoWoS Lock & ASML Raises Guidance

**Jayne Cole** (0:00)
AI Hardware and Chips Daily News.
I'm Jayne Cole. Thanks for joining me.
Today Intel Foundry's 85% yield, second source reality or margin trap. Intel's Foundry just crossed 85% yield on its 18A node, and that number matters more than almost anything else in the Foundry business right now. 85% is the threshold where merchant Foundry economics actually work. Below it, you can demonstrate technical capability. Above it, you can sustain external customers at volume. Intel is now above it, and the design win list reads like a who's who of AI infrastructure. Nvidia, Google, AMD, Microsoft, Apple, Marvell, OpenAI.
That's the headline. Here's what to watch underneath it. Design wins and production ramps are two different things. The confirmed wins lack explicit volume commitments or ramp timelines. Intel still trails TSMC's N2 by roughly five percentage coins on yield. An analyst estimates put a ceiling of around 20% growth for the foundry business at current trajectory. The important distinction is between customer optionality and customer commitment. Hyperscalers naming Intel as a qualified second source is strategically significant. Hyperscalers actually shifting meaningful volume is a different proof point, and that confirmation hasn't arrived yet. The incentive structure though is real. These customers have been looked into a single supplier for both logic and packaging. That concentration creates risk they'd prefer not to carry indefinitely. Intel reaching commercial viability on 18A gives them a credible alternative for the first time in years. Whether they use it aggressively or sparingly is the unresolved question. The packaging story may actually be more immediately significant. Intel's Emib-T advanced packaging has hit 98% yield, matching TSMC's CoAS technology. That's not parity in theory. It's already in production volume across Nvidia's Feynman platform, Google's TPU HumuFish, and AWS Trainium 3
CoAS has been the real choke point. Wafers supply gets the coverage, but packaging allocation is what actually constrained AI infrastructure deployments. A second source at 98% yield, already adopted by the three largest AI infrastructure builders, changes the leverage dynamic meaningfully. TSMC no longer has a monopoly on the integration layer.
Here's the thing. Stepping back to the equipment layer, ASML raised its full year 2026 guidance sharply, lifting sales to between 43 and 45 billion euros, from a prior range of 36 to 40 billion. Gross margin guidance moved to 54 to 56 percent. ASML also committed to a 30 percent capacity increase across both low NA-UV and DUV systems. The signal here is that AI capital expenditure isn't softening at the infrastructure layer. Equipment supplies with genuine pricing power are seeing visibility strong enough to expand capacity. That eliminates equipment supplies and near-term constraint, which shifts bottleneck risk back to fab execution and yield. On-memory architecture, two research teams, one from Unist in Korea and one from the University of Tokyo, have proposed vertical DRM designs that go beyond what HBM4 and HBM5 can deliver. The Unist V die and Tokyo's mosaic architecture, both stack dies vertically rather than horizontally, achieving four times more interconnects than HBM4, 37 percent lower latency and triple the thermal conductivity.
These are pre-commercial. Neither has demonstrated manufacturing yield or cost efficiency at scale.
But the research signals something the industry has been circling. Conventional HBM stacking is approaching a thermal and physical ceiling, and the next architecture shift is already visible on the academic horizon. Consider this. Nvidia's on-automotive chief disclosed that Jensen Huang personally arbitrates weekly disputes over internal GPU compute allocation. That single detail tells you more about supply constraints than any quarterly filing. When the dominant GPU supplier can't internally satisfy demand across its own business units, the scarcity is structural, not a queue management problem.
TSMC reports on July 16th, the market is pricing in a gross margin around 67%, potentially touching 70%. If it misses, the read-through isn't just on TSMC's pricing power. It raises questions about whether the supply constrained premium the entire AI hardware supply chain is currently carrying can hold.
The near-term signals to track are simple. Intel's design wins converting to volume commitments, TSMC's margin print and capex guidance, and whether EMIBT adoption by hyperscalers accelerates or plateaus. Those three data points will clarify whether this is a genuine competitive restructuring of the foundry layer or a more gradual shift than the yield numbers currently imply. Thanks for listening. This podcast was built using AI technology, a YesOui production.