TSMC Concedes Intel’s EMIB Packaging Is A Potent Contender, Starts Building “Quasi-EMIB” As CoWoS Remains Choked Through 2026

**Skyler Monroe** (0:10)
Hey everyone, welcome back to the AI Hardware Show. I'm your host Skyler Monroe. And if you're into chips, silicon and the hardware that's making AI possible, you are absolutely in the right place. Big thanks to our sponsors today. Ada, helping businesses integrate AI into their workflows in ways that actually stick. Ago Consulting, that's Ago, your go-to for silicon development consulting from AI to so sick. And Zen Semiconductor, the umbrella company building the processors and AI fabric behind modern data centers, with ventures like their Sierra RISC-V CPUs and Loom AI fabric. Plus Ada for deploying AI at scale in any business. Today, we're talking advanced packaging drama between TSMC and Intel, the tightening vice on Nvidia's China business, and a hidden risk for Nvidia that might be bigger than anything AMD or Broadcom could throw at them. Let's get into it. Alright, story one, and this one genuinely has me excited, because it's a fascinating dynamic playing out in the advanced packaging world. TSMC, the undisputed king of chip fabrication, is apparently borrowing a page from Intel's playbook.
Specifically, they're developing what they're calling internally a Quasi-EmiB, which is inspired by Intel's embedded multi-die interconnect bridge technology. Now, that is a headline I did not have on my bingo card for this year, so let's back up and set the scene here. TSMC has this packaging technology called CoWoS, chip-on-wafer-on-substrate. It's been their flagship advanced packaging solution, and it's been absolutely critical for AI chips.
When you're building something like an Nvidia H100 or H200, you need to stitch together the GPU die with HBM memory in a way that gives you massive bandwidth.
CoWoS does that using a silicon interposer, basically a big slice of silicon that sits between all the chiplets and connects them with incredibly dense wiring. The problem is that silicon interposer is large, and I mean large in a way that creates real manufacturing headaches. Think of it like trying to cut a huge pizza out of a fixed size dough. The bigger your slice, the fewer slices you get from the same dough, and the more likely you are to hit a defect. So CoWoS capacity has been brutally constrained. We're talking backlogs stretching well into 2026
If you're a company trying to build AI hardware right now, that's a painful bottleneck. Intel's IMIB takes a fundamentally different approach. Instead of one massive silicon interposer spanning the whole package, IMIB uses small targeted silicon bridges, little chips embedded right into the package substrate placed only where you actually need high bandwidth connections between dies. It's surgical rather than broad. Think of it like the difference between repaving an entire highway versus just patching the specific intersections where congestion happens.
And here's the thing, because IMIB bridges are small and targeted, they're cheaper to manufacture, easier to scale, and don't create the same kind of capacity crunch.
Intel has been using IMIB in its own products for years, and now external customers are starting to notice. With TSMC's co-host slots so hard to come by, some chip designers are looking at Intel Foundry's IMIB as a real alternative. So what does TSMC do? They're reportedly building their own version. The quasi-IMIB approach, borrowing the core concept of localized silicon bridges embedded in the substrate rather than a full silicon interposer. Now, TSMC isn't just copying blindly here, they have their own engineering chops and they'll put their own spin on it, but the directional shift is significant. This matters for a few reasons. First, it's validation for Intel. Intel Foundry has had a rough few years losing ground on process nodes struggling with yields, but in advanced packaging, they've had something genuinely differentiated. Having TSMC essentially acknowledged that by moving toward a similar architecture that's meaningful recognition, second, it could eventually help alleviate the supply crunch. If TSMC can produce advanced packages without needing those giant yield-killing interposers, they can potentially ramp capacity faster. That's good news for the entire AI chip ecosystem. Nvidia, AMD, all the custom silicon folks, anyone who's been stuck in the CoWAS waitlist. Third, this is a reminder that the packaging layer has become just as strategically important as the fab process itself. We spent years talking about who's going to hit 3nm, 2nm, and all of that still matters enormously. But the ability to take multiple chiplets and connect them efficiently in a package? That's a competitive battleground now, too.
TSMC building a quasi-EMIB is proof of that. The packaging wars are real, folks. Okay, stories 2 and 3 are deeply connected, so I'm going to take them together.
We've got two data points this week that paint a pretty clear picture of what's happening with Nvidia and China.
First, Nvidia has reportedly cut more than half of the Asian buyers from its AI chip whitelist as part of a China crackdown. Second, a US trade official has confirmed that very few their words, very few Nvidia H200 chips have actually made it into China. Let's start with the whitelist situation. Nvidia maintains a list of approved buyers in Asia companies that can purchase their AI chips, particularly the more restricted ones. And apparently, that list has been dramatically pruned. More than half of the Asian buyers have been removed. Now, this isn't Nvidia being capricious. This is almost certainly the result of pressure from US export controls and the enforcement machinery around them getting sharper.