Ep. 019 - Inside the STEEL Lab: From Package to Transistor (Teardown Lab) | Afzal Ahmad, Andrew Wagner, Jordan Nanos

**Jordan Nanos** (0:04)
Hello, everyone, welcome back to Semi Analysis Weekly, episode number 19 We're here with the STEEL team.
One of the coolest things, actually, I would say definitely the coolest thing that Semi Analysis is doing right now, the STEEL Teardown Lab. We're going to dig into the public launch of STEEL. That means an article where we did a teardown of some consumer chips and basically put on display everything that the STEEL team has to offer. Joining me today, we've got Andrew. How's it going, man? Welcome to the show.

**Andrew Wagner** (0:35)
Thanks for having me.

**Jordan Nanos** (0:38)
We've got Afzal. Welcome.

**Afzal Ahmad** (0:40)
Thank you. Hello.

**Jordan Nanos** (0:43)
Awesome, guys. I think a lot of the listeners are going to need some basic control. Hopefully, you can bear with me as we go through this and explain some things to the general audience.
Let's start with this. Wags, can you tell me what's the STEEL team and what is a teardown high level?

**Andrew Wagner** (1:03)
What is a teardown? It's literally what it sounds like.
In the case of our first article, consumer chip, we take out the package and we just start breaking it down and looking at what's there. We take it from the box we get it in, all the way down to the transistor and everything in between. Anyone listening understands data center, AI, consumer chips, everything's advancing at the speed of light, right? In some cases, literally. And so, there's a lot of competition within the marketplace. Who's in, who's out? What are the advances? What are the technical nuances of every technology? Competitors are curious on how their competitors are within the same boundary conditions. How are they making decisions and how are they advancing their technology? And so, a teardown goes into every aspect of that. Materials, process, integration, electrical engineering, architecture, design. Every kind of piece of that puzzle that we can look at, that's what we're spinning up this lab, the STEEL, and that's what we're doing. And so, our first article that came out a few weeks ago is kind of the first taste of what's possible, what we're capable of.

**Jordan Nanos** (2:12)
Awesome. Yeah, it was a great article and we'll definitely dig into it. So I want to get your take on this.
When it comes to teardowns, before STEEL existed, obviously people would use these outputs that STEEL can produce in order to understand chips. Can you explain a little bit about the motivation of what you use the output from the STEEL Lab to do in order to understand chips?

**Afzal Ahmad** (2:35)
Well, there's really two angles you can approach this from. One is from the chip designers themselves, and one is as a competitor.
So, for example, if I have the tie-down of the NVIDIA GPU, I can see how they are using the area, how much cache they are using, how much area is being used for the compute or for the memory or the IO. So that's one major thing for them. And on the other side, for the chip designers themselves, they get to see what the process node is, for example, before they even start designing. So they can see this chip from Apple, then you can see, this is what TSMC N3 looks like, this is what FinFlex looks like, and then we can, this is our goal for, when we actually make our own chips.

**Jordan Nanos** (3:21)
Awesome. So can you tell me a little more about exactly this article, obviously in the title, talks about SMIC N plus three, as well as Huawei's Kirin 9030 So that's both the process technology and then the chip itself that you might be analyzing. Can you walk me through like a little bit of the high level of what you guys learned in the process of tearing down the chip?

**Afzal Ahmad** (3:45)
First, let's go through some context. So in 2021, they were, SMIC started fabricating their own N plus one node, which was roughly equivalent to an eight nanometer-ish node. But the one of the main problems, it didn't have any SRAM. So it couldn't be used for any big smartphone chips or even AI accelerators.
But now, then two years later, there is N plus two, which they use in a lot of their smartphone chips, and they're going to be using in their new Ascent G. So now, we come to N plus three, which is the newest one that they just started using for smartphones. N plus three is the shrink of the previous two generations, but the main thing is firstly the M zero, which is the lowest metal layer, has shrunk a lot. It went over about 15 plus percent. Then you have the higher layers, which aren't so much. But on the transistor level itself, there are so many major changes. And I guess one of the biggest things for our use case, I mean, for their use case, I guess, is that the SRAM is much smaller now.